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| CY8C24123 CY8C24223, CY8C24423 PSoC(R) Programmable System-on-ChipTM Features Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 3.0 to 5.25 V Operating Voltage Operating Voltages Down to 1.0V Using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Advanced Peripherals (PSoC Blocks) Six Rail-to-Rail Analog PSoC Blocks Provide: * Up to 14-Bit ADCs * Up to 8-Bit DACs * Programmable Gain Amplifiers * Programmable Filters and Comparators Four Digital PSoC Blocks Provide: * 8 to 32-Bit Timers, Counters, and PWMs * CRC and PRS Modules * Full-Duplex UART * Multiple SPITM Masters or Slaves * Connectable to all GPIO Pins Complex Peripherals by Combining Blocks Precision, Programmable Clocking Internal 2.5% 24/48 MHz Oscillator High-Accuracy 24 MHz with Optional 32 kHz Crystal and PLL Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep Flexible On-Chip Memory 4K Bytes Flash Program Storage 50,000 Erase/Write Cycles 256 Bytes SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Programmable Pin Configurations 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 10 Analog Inputs on GPIO Two 30 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO Additional System Resources 2 I CTM Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoC DesignerTM) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory Logic Block Diagram Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM 256 Bytes Interrupt Controller Global Analog Interconnect Flash 4K Sleep and Watchdog SROM CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array (1 Rows, 4 Blocks) ANALOG SYSTEM Analog Block Array (2 Columns, 6 Blocks) Analog Ref Analog Input Muxing Digital Clocks Multiply Accum. POR and LVD Decimator I2C System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 38-12011 Rev. *G * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised December 11, 2008 [+] Feedback CY8C24123 CY8C24223, CY8C24423 PSoC(R) Functional Overview The PSoC(R) family consists of many Mixed Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, as shown in the Logic Block Diagram on page 1, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C24x23 family can have up to three IO ports that connect to the global digital and analog interconnects, providing access to four digital blocks and 6 analog blocks. Digital System The Digital System is composed of four digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure 1. Digital System Block Diagram Port 2 Port 1 Port 0 Digital Clocks From Core To System Bus To Analog System DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration 8 8 Row 0 DBB00 DBB01 DCB02 4 DCB03 4 8 8 Row Output Configuration PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 11 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 4 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations include: PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8-bit with selectable parity (up to one) SPI master and slave (up to one) I2C slave and master (one available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to one) Pseudo Random Sequence Generators (8 to 32 bit) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are listed in the table PSoC Device Characteristics on page 4. Document Number: 38-12011 Rev. *G Page 2 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Analog System The Analog System is composed of six configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are: Figure 2. Analog System Block Diagram P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] Analog-to-digital converters (up to two, with 6 to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (two and four pole band-pass, low-pass, and notch) Amplifiers (up to two, with selectable gain to 48x) Instrumentation amplifiers (one with selectable gain to 93x) Comparators (up to two, with 16 selectable thresholds) DACs (up to two, with 6 to 9-bit resolution) Multiplying DACs (up to two, with 6- to 9-bit resolution) High current output drivers (two with 30 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF dialer Modulators Correlators Peak detectors Many other topologies possible P2[3] P2[4] P2[2] P2[0] P2[1] Array Input Configuration ACI0[1:0] ACI1[1:0] Block Array ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks. The number of blocks is dependant on the device family which is detailed in the table PSoC Device Characteristics on page 4. Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 38-12011 Rev. *G Page 3 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource follow: Getting Started The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, refer the PSoC Programmable Sytem-on-Chip Technical Reference Manual. For up-to-date Ordering, Packaging, and Electrical Specification information, refer the latest PSoC device data sheets on the web at http://www.cypress.com/psoc. Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. Technical Training Free PSoC technical training is available for beginners and is taught by a marketing or application engineer over the phone. PSoC training classes cover designing, debugging, advanced analog, and application-specific classes covering topics, such as PSoC and the LIN bus. Go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select Technical Training for more details. PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. The following table lists the resources available for specific PSoC device groups. Table 1. PSoC Device Characteristics Analog Columns Analog Outputs Analog Inputs Analog Blocks PSoC Part Number Digital Blocks Digital IO Digital Rows Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants. Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support. CY8C29x66 up to 4 64 CY8C27x66 up to 2 44 CY8C27x43 up to 2 44 CY8C24x23 up to 1 24 CY8C22x13 up to 1 16 16 8 8 4 4 12 12 12 12 8 4 4 4 2 1 4 4 4 2 1 12 12 12 6 3 Application Notes A long list of application notes can assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are listed by date as default. Document Number: 38-12011 Rev. *G Page 4 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Development Tools The Cypress MicroSystems PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows 98, Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP (refer Figure 3). PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. Figure 3. PSoC Designer Subsystems PSoC Designer Software Subsystems Device Editor The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. PSoC Designer sets up power on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. After the framework is generated, the user can add application-specific code to flesh out the framework. It is also possible to change the selected components and regenerate the framework. Design Browser The Design Browser allows users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. Application Editor PSoC TM Designer Graphical Designer Interface Context Sensitive Help Commands Results Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet PSoCTM Designer Core Engine In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports Cypress MicroSystems' PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Manufacturing Information File Emulation Pod In-Circuit Emulator Device Programmer Document Number: 38-12011 Rev. *G Page 5 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. User Modules and the PSoC Development Process The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides high-level functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a pictorial environment (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. Hardware Tools In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the parallel or USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Figure 4. PSoC Development Tool Kit Document Number: 38-12011 Rev. *G Page 6 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Figure 5. User Module and Source Code Development Flows Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Table 2. Acronyms Acronym AC alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current ADC API CPU CT DAC DC Description Device Editor User Module Selection Placement and Parameter -ization Source Code Generator Generate Application Application Editor Project Manager Source Code Editor Build Manager EEPROM electrically erasable programmable read-only memory FSR Build All full scale range general purpose IO input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter power on reset precision power on reset Programmable System-on-Chip pulse width modulator random access memory read only memory switched capacitor switch mode pump GPIO IO IPOR LSb Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager LVD MSb PC POR PPOR The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a ROM file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the ROM image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. PSoC(R) PWM RAM ROM SC SMP Units of Measure A units of measure table is located in the Electrical Specifications section. Table 7 on page 11 lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal. Document Number: 38-12011 Rev. *G Page 7 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Pinouts The CY8C24x23 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 8-Pin Part Pinout Table 3. 8-Pin Part Pinout (PDIP, SOIC) Type Pin Pin No. Digital Analog Name 1 2 3 4 5 6 7 8 IO IO IO Power I I IO IO IO Power IO IO P0[5] P0[3] P1[1] Vss P1[0] P0[2] P0[4] Vdd Description Analog column mux input and column output Analog column mux input and column output Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection Crystal Output (XTALout), I2C Serial Data (SDA) Analog column mux input Analog column mux input Supply voltage Figure 6. CY8C24123 8-Pin PSoC Device AIO, P0[5] AIO, P0[3] I2C SCL, XTALin, P1[1] Vss 8 1 2 PDIP 7 3SOIC6 5 4 Vdd P0[4], AI P0[2], AI P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. 20-Pin Part Pinout Table 4. 20-Pin Part Pinout (PDIP, SSOP, SOIC) Type Pin Pin No. Digital Analog Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IO IO IO IO Power IO IO IO IO Input I I I I IO IO IO IO Power IO IO IO IO Power I IO IO I P0[7] P0[5] P0[3] P0[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES Active high external reset with internal pull down P0[0] P0[2] P0[4] P0[6] Vdd Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage Optional External Clock Input (EXTCLK) Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection Crystal Output (XTALout), I2C Serial Data (SDA) Description Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Switch Mode Pump (SMP) connection to external components required I2C Serial Clock (SCL I2C Serial Data (SDA) Figure 7. CY8C24223 20-Pin PSoC Device AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 PDIP SSOP SOIC 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. Document Number: 38-12011 Rev. *G Page 8 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 28-Pin Part Pinout Table 5. 28-Pin Part Pinout (PDIP, SSOP, SOIC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Type Pin Description Digital Analog Name IO I P0[7] Analog column mux input IO IO P0[5] Analog column mux input and column output IO IO P0[3] Analog column mux input and column output IO I P0[1] Analog column mux input. IO P2[7] IO P2[5] IO I P2[3] Direct switched capacitor block input IO I P2[1] Direct switched capacitor block input Power SMP Switch Mode Pump (SMP) connection to external components required IO P1[7] I2C Serial Clock (SCL) IO P1[5] I2C Serial Data (SDA) IO P1[3] IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) Power Vss Ground connection IO P1[0] Crystal Output (XTALout), I2C Serial Data (SDA) IO P1[2] IO P1[4] Optional External Clock Input (EXTCLK) IO P1[6] Input XRES Active high external reset with internal pull down IO I P2[0] Direct switched capacitor block input IO I P2[2] Direct switched capacitor block input IO P2[4] External Analog Ground (AGND) IO P2[6] External Voltage Reference (VRef) IO I P0[0] Analog column mux input IO I P0[2] Analog column mux input IO I P0[4] Analog column mux input IO I P0[6] Analog column mux input Power Vdd Supply voltage Figure 8. CY8C24423 28-Pin PSoC Device AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI, P2[3] AI, P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PDIP SSOP SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. Document Number: 38-12011 Rev. *G Page 9 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 32-Pin Part Pinout Table 6. 32-Pin Part Pinout (MLF*) Type Pin No. Digital Analog 1 IO 2 IO 3 IO I 4 IO I 5 Power 6 Power Pin Name P2[7] P2[5] P2[3] P2[1] Vss SMP Description Figure 9. CY8C24423 32-Pin PSoC Device P0[1], AI P0[3], AIO P0[5], AIO P0[7], AI Vdd P0[6], AI P2[7] P2[5] AI, P2[3] AI, P2[1] Vss SMP I2C SCL, P1[7] I2C SDA, P1[5] 1 2 3 4 5 6 7 8 P0[4], AI NC 24 23 22 21 20 19 18 17 P0[2], AI P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Power IO IO IO Vss P1[0] P1[2] P1[4] Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection Crystal Output (XTALout), I2C Serial Data (SDA) Optional External Clock Input (EXTCLK) No connection. Do not use. IO Input IO IO IO IO IO IO IO IO Power IO IO IO IO I IO IO I I I I I I I NC P1[6] XRES Active high external reset with internal pull down P2[0] Direct switched capacitor block input P2[2] Direct switched capacitor block input P2[4] External Analog Ground (AGND) P2[6] External Voltage Reference (VRef) P0[0] Analog column mux input P0[2] Analog column mux input NC No connection. Do not use. P0[4] Analog column mux input P0[6] Analog column mux input Vdd Supply voltage P0[7] Analog column mux input P0[5] Analog column mux input and column output P0[3] Analog column mux input and column output P0[1] Analog column mux input LEGEND: A = Analog, I = Input, and O = Output. * The MLF package has a center pad that must be connected to the same ground as the Vss pin. Document Number: 38-12011 Rev. *G NC P1[3] I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] NC 7 8 9 10 11 IO IO IO IO P1[7] P1[5] NC P1[3] P1[1] Direct switched capacitor block input Direct switched capacitor block input Ground connection Switch Mode Pump (SMP) connection to external components required I2C Serial Clock (SCL) I2C Serial Data (SDA) No connection. Do not use. 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 MLF (Top View) Page 10 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Register Reference This section lists the registers of the CY8C27xxx PSoC device by way of mapping tables, in offset order. For detailed register information, reference the PSoC Programmable System-on-Chip Technical Reference Manual. Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is also referred to as IO space and is broken into two parts. The XOI bit in the Flag register determines which bank the user is currently in. When the XOI bit is set, the user is said to be in the "extended" address space or the "configuration" registers. Note In the following register mapping tables, blank fields are Reserved and must not be accessed. Register Conventions Abbreviations Used The register conventions specific to this section are listed in the following table. Table 7. Abbreviations Convention RW R W L C # Description Read and write register or bit(s) Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Document Number: 38-12011 Rev. *G Page 11 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Table 8. Register Map Bank 0 Table: User Space Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name Access PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F RW RW RW RW RW RW RW RW RW RW RW RW 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F RW RW RW RW RW RW RW RW C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F RW RW RW RW RW RW RW RW I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC INT_CLR3 INT_MSK3 DD DE DF INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED RW RW RC W RC RC RW RW W W R R RW RW RW RW RW # RW # RW RW DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D # W RW # # W RW # # W RW # # W AMX_IN 60 61 62 RW A0 A1 A2 ARF_CR CMP_CR0 ASY_CR CMP_CR1 63 64 65 66 67 68 69 6A 6B 6C 6D RW # # RW A3 A4 A5 A6 A7 A8 A9 AA AB AC AD # Access is bit specific. Blank fields are Reserved and must not be accessed. Document Number: 38-12011 Rev. *G Page 12 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Table 8. Register Map Bank 0 Table: User Space (continued) Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name Access DCB03DR2 DCB03CR0 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW # ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDIOLT1 RDI0RO0 RDI0RO1 AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. RW RW RW RW RW RW RW ACC_DR3 ACC_DR2 EE EF F0 F1 F2 F3 F4 F5 F6 RW RW CPU_F F7 F8 F9 FA FB FC FD RL CPU_SCR1 CPU_SCR0 FE FF # # Blank fields are Reserved and must not be accessed. Table 9. Register Map Bank 1 Table: Configuration Space Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 RW RW RW RW RW RW RW RW RW RW RW RW 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F RW RW RW RW RW RW RW RW C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 90 91 92 93 94 95 96 RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU D0 D1 D2 D3 D4 D5 D6 RW RW RW RW Blank fields are Reserved and must not be accessed. # Access is bit specific. Document Number: 38-12011 Rev. *G Page 13 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Table 9. Register Map Bank 1 Table: Configuration Space (continued) Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name 17 18 19 1A 1B 1C 1D 1E 1F DBB00FN DBB00IN DBB00OU 20 21 22 23 DBB01FN DBB01IN DBB01OU 24 25 26 27 DCB02FN DCB02IN DCB02OU 28 29 2A 2B DCB03FN DCB03IN DCB03OU 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Blank fields are Reserved and must not be accessed. 57 58 59 5A 5B 5C 5D 5E 5F RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 RW RW RW AMD_CR1 ALT_CR0 RW RW RW 60 61 62 63 64 65 66 67 68 69 6A 6B RW RW RW 6C 6D 6E 6F ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RW D7 D8 D9 DA DB DC OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 IMO_TR ILO_TR BDG_TR ECO_TR E8 E9 EA EB EC ED EE EF W W RW W RW RW RW RW RW RW RW R RDI0RI RDI0SYN RDI0IS RDI0LT0 RDIOLT1 RDI0RO0 RDI0RO1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW CPU_F F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD CPU_SCR1 CPU_SCR0 FE FF # # RL # Access is bit specific. Document Number: 38-12011 Rev. *G Page 14 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C24x23 PSoC device. For latest electrical specifications, http://www.cypress.com. Specifications are valid for -40oC TA 85oC and TJ 100oC, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40oC TA 70oC and TJ 82oC. Figure 10. Voltage versus Operating Frequency 5.25 4.75 Vdd Voltage 3.00 93 kHz CPU Frequency The following table lists the units of measure that are used in this section. Table 10. Units of Measure Symbol C dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm micro ampere micro farad micro henry microsecond micro volts micro volts root-mean-square Symbol W mA ms mV nA ns nV W pA pF pp ppm ps sps s V Unit of Measure micro watts milli-ampere milli-second milli-volts nano ampere nanosecond nanovolts ohm pico ampere pico farad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts lid ng Va rati n pe io O Reg 12 MHz 24 MHz Document Number: 38-12011 Rev. *G Page 15 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 11. Absolute Maximum Ratings Symbol Description TSTG Storage Temperature TA Vdd VIO - IMIO IMAIO - - Min -55 Typ - - - - - - - - - Units Notes o C Higher storage temperatures reduce data retention time. o +85 C +6.0 V Vdd + 0.5 V Vdd + 0.5 V +50 mA +50 mA - 200 V mA Max +100 Ambient Temperature with Power Applied -40 Supply Voltage on Vdd Relative to Vss -0.5 DC Input Voltage Vss - 0.5 DC Voltage Applied to Tri-state Vss - 0.5 Maximum Current into any Port Pin -25 Maximum Current into any Port Pin Configured -50 as Analog Driver Static Discharge Voltage 2000 Latch-up Current - Operating Temperature Table 12. Operating Temperature Symbol Description TA Ambient Temperature TJ Junction Temperature Min -40 -40 Typ - - Max +85 +100 Units Notes oC oC The temperature rise from ambient to junction is package specific. See Thermal Impedances per Package on page 41. The user must limit the power consumption to comply with this requirement. Document Number: 38-12011 Rev. *G Page 16 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 13. DC Chip-Level Specifications Symbol Description Vdd Supply Voltage IDD Supply Current Min 3.00 - Typ - 5 Max 5.25 8 Units Notes V mA Conditions are Vdd = 5.0V, 25 oC, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. mA Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, 48 MHz = Disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. A Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC <= TA <= 55 oC. A Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA <= 85 oC. A Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC <= TA <= 55 oC. A Conditions are with properly loaded, 1W max, 32.768 kHz crystal. Vdd = 3.3 V, 55 oC < TA <= 85 oC. V Trimmed for appropriate Vdd. IDD3 Supply Current - 3.3 6.0 ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.a Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.a Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.a Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.a Reference Voltage (Bandgap) - 3 6.5 ISBH - 4 25 ISBXTL - 4 7.5 ISBXTLH - 5 26 VREF 1.275 1.3 1.325 a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar functions enabled. Document Number: 38-12011 Rev. *G Page 17 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 DC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 14. DC GPIO Specifications Symbol Description RPU Pull up Resistor Pull down Resistor RPD High Output Level VOH Min 4 4 Vdd - 1.0 Typ 5.6 5.6 - Max 8 8 - Units Notes k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (80 mA maximum combined IOH budget) V IOL = 25 mA, Vdd = 4.75 to 5.25V (150 mA maximum combined IOL budget) V Vdd = 3.0 to 5.25 V Vdd = 3.0 to 5.25 mV nA Gross tested to 1 A pF Package and pin dependent. Temp = 25oC pF Package and pin dependent. Temp = 25oC VOL Low Output Level - - 0.75 VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - 2.1 - - - - - - 60 1 3.5 3.5 0.8 - - 10 10 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25C and are for design guidance only. Table 15. 5V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Low Power Input Offset Voltage (absolute value) Mid Power Input Offset Voltage (absolute value) High Power TCVOSOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) IEBOA Input Capacitance (Port 0 Analog Pins) CINOA Min - - - - - - Typ 1.6 1.3 1.2 7.0 20 4.5 Max 10 8 7.5 35.0 - 9.5 Units mV mV Notes VCMOA Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias) 0.0 0.5 - - mV V/oC pA Gross tested to 1 A. pF Package and pin dependent. Temp = 25oC. Vdd V The common-mode input Vdd - 0.5 voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Document Number: 38-12011 Rev. *G Page 18 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Table 15. 5V DC Operational Amplifier Specifications (continued) Symbol GOLOA Description Open Loop Gain Power = Low Power = Medium Power = High Min 60 60 80 Typ - Max - Units Notes dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. V V V V V V A A A A A A dB VOHIGHOA High Output Voltage Swing (worst case internal load) Vdd - 0.2 Power = Low Vdd - 0.2 Power = Medium Vdd - 0.5 Power = High VOLOWOA Low Output Voltage Swing (worst case internal load) Power = Low - Power = Medium - Power = High - ISOA Supply Current (including associated AGND buffer) Power = Low - Power = Low, Opamp Bias = High - - Power = Medium - Power = Medium, Opamp Bias = High Power = High - Power = High, Opamp Bias = High - PSRROA Supply Voltage Rejection Ratio 60 - - - - - - 150 300 600 1200 2400 4600 - - - - 0.2 0.2 0.5 200 400 800 1600 3200 6400 - Document Number: 38-12011 Rev. *G Page 19 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Table 16. 3.3V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Low Power Input Offset Voltage (absolute value) Mid Power High Power is 5 Volt Only Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Min - - - - - 0.2 Typ 1.65 1.32 7.0 20 4.5 - Max 10 8 35.0 - 9.5 Vdd - 0.2 Units mV mV V/oC pA pF V Gross tested to 1 A. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. Notes TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA GOLOA Open Loop Gain Power = Low Power = Medium Power = High - 60 60 80 - dB VOHIGHOA High Output Voltage Swing (worst case internal load) Power = Low Power = Medium Power = High is 5V only VOLOWOA Low Output Voltage Swing (worst case internal load) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High Supply Voltage Rejection Ratio Vdd - 0.2 Vdd - 0.2 Vdd - 0.2 - - - - - - - - - 50 - - - - - - 150 300 600 1200 2400 4600 - - - - 0.2 0.2 0.2 200 400 800 1600 3200 6400 - V V V V V V A A A A A A dB PSRROA Document Number: 38-12011 Rev. *G Page 20 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 17. 5V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio Table 18. 3.3V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High VOLOWOB Low Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio Min - - 0.5 - - 0.5 x Vdd + 1.0 0.5 x Vdd + 1.0 - - Typ 3 +6 1 1 - - - - 0.8 2.0 - Max 12 - Vdd - 1.0 - - - - 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 2.0 4.3 - Units mV V/C V W W V V V V mA mA dB Min - - 0.5 - - 0.5 x Vdd + 1.1 0.5 x Vdd + 1.1 - - - - 60 Typ 3 +6 - 1 1 - - - - 1.1 2.6 - Max 12 - Vdd - 1.0 - - - - 0.5 x Vdd - 1.3 0.5 x Vdd - 1.3 5.1 8.8 - Units mV V/C V W W V V V V mA mA dB - 50 Document Number: 38-12011 Rev. *G Page 21 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 19. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP 5V VPUMP 3V IPUMP Description 5V Output voltage 3V Output voltage Available Output Current VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.8V, VPUMP = 5.0V Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump Line Regulation (over VBAT range) Load Regulation Min 4.75 3.00 8 5 1.8 1.0 1.1 - - - 35 - - Typ 5.0 3.25 - - - - - 5 5 25 50 1.3 50 Max 5.25 3.60 - - 5.0 3.3 - - - - - - - Units V V mA mA V V V %VOa %VOa mVpp % MHz % Configuration of note 2, load is 5mA Configuration of note 2, load is 5mA, Vout is 3.25V. Notes Average, neglecting ripple Average, neglecting ripple For implementation, which includes 2 uH inductor, 1 uF cap, and Schottky diode VBAT5V VBAT3V VBATSTART VPUMP_Line VPUMP_Load VPUMP_Ripple Output Voltage Ripple (depends on cap/load) - FPUMP DCPUMP Efficiency Switching Frequency Switching Duty Cycle a. VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 23 on page 25. Figure 11. Basic Switch Mode Pump Circuit D1 Vdd C1 SMP Battery VBAT + PSoCTM Vss Document Number: 38-12011 Rev. *G Page 22 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND. Table 20. 5V DC Analog Reference Specifications Symbol BG - - - - - - Description Bandgap Voltage Reference AGND = Vdd/2a CT Block Power = High AGND = 2 x BandGapa CT Block Power = High AGND = P2[4] (P2[4] = Vdd/2)a CT Block Power = High AGND = BandGapa CT Block Power = High AGND = 1.6 x BandGapa CT Block Power = High AGND Column to Column Variation (AGND = Vdd/2)a CT Block Power = High RefHi = Vdd/2 + BandGap Ref Control Power = High RefHi = 3 x BandGap Ref Control Power = High RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) Ref Control Power = High RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Ref Control Power = High Min 1.274 Vdd/2 - 0.043 2 x BG - 0.048 P2[4] - 0.013 BG - 0.009 1.6 x BG - 0.022 -0.034 Typ 1.30 Vdd/2 - 0.025 2 x BG - 0.030 P2[4] BG + 0.008 1.6 x BG - 0.010 0.000 Max 1.326 Vdd/2 + 0.003 2 x BG + 0.024 P2[4] + 0.014 BG + 0.016 1.6 x BG + 0.018 0.034 Units V V V V V V V - Vdd/2 + BG - 0.140 Vdd/2 + BG - 0.018 Vdd/2 + BG + V 0.103 - - 3 x BG - 0.112 2 x BG + P2[6] 0.113 3 x BG - 0.018 2 x BG + P2[6] 0.018 3 x BG + 0.076 2 x BG + P2[6] + 0.077 V V - - P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 P2[4] + P2[6] 0.016 3.2 x BG P2[4] + P2[6]+ 0.100 3.2 x BG + 0.076 V V RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.133 Ref Control Power = High RefHi = 3.2 x BandGap Ref Control Power = High RefLo = Vdd/2 - BandGap Ref Control Power = High RefLo = BandGap Ref Control Power = High RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) Ref Control Power = High RefLo = P2[4] - BandGap (P2[4] = Vdd/2) Ref Control Power = High - - - - 3.2 x BG - 0.112 Vdd/2 - BG - 0.051 V V V V Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.098 BG - 0.082 2 x BG - P2[6] 0.084 P2[4] - BG - 0.056 BG + 0.023 2 x BG - P2[6] + 0.025 BG + 0.129 2 x BG - P2[6] + 0.134 - - P2[4] - BG + 0.026 P2[4] - BG + 0.107 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110 V V RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.057 Ref Control Power = High a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 2%. Document Number: 38-12011 Rev. *G Page 23 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Table 21. 3.3V DC Analog Reference Specifications Symbol Description BG Bandgap Voltage Reference - AGND = Vdd/2a CT Block Power = High - AGND = 2 x BandGapa CT Block Power = High - AGND = P2[4] (P2[4] = Vdd/2) CT Block Power = High - AGND = BandGapa CT Block Power = High - AGND = 1.6 x BandGapa CT Block Power = High - AGND Column to Column Variation (AGND = Vdd/2)a CT Block Power = High - RefHi = Vdd/2 + BandGap Ref Control Power = High - RefHi = 3 x BandGap Ref Control Power = High - RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Ref Control Power = High - RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Ref Control Power = High - RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Ref Control Power = High - - - - - - RefHi = 3.2 x BandGap Ref Control Power = High RefLo = Vdd/2 - BandGap Ref Control Power = High RefLo = BandGap Ref Control Power = High RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Ref Control Power = High RefLo = P2[4] - BandGap (P2[4] = Vdd/2) Ref Control Power = High RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Ref Control Power = High Min 1.274 Vdd/2 - 0.037 Typ 1.30 Max 1.326 Units V V Vdd/2 - 0.020 Vdd/2 + 0.002 Not Allowed P2[4] - 0.008 BG - 0.009 1.6 x BG - 0.027 -0.034 P2[4] + 0.001 BG + 0.005 1.6 x BG - 0.010 0.000 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + 0.009 BG + 0.015 1.6 x BG + 0.018 0.034 V V V mV P2[4] + P2[6] 0.075 P2[4] + P2[6] P2[4] + P2[6] + 0.009 0.057 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed V P2[4] - P2[6] 0.048 P2[4]- P2[6] + 0.022 P2[4] - P2[6] + 0.092 V a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 2% Document Number: 38-12011 Rev. *G Page 24 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 22. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) Min - - Typ 12.24 80 Max - - Units k fF DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip Technical Reference Manual for more information on the VLT_CR register. Table 23. DC POR and LVD Specifications Symbol Description Min Typ 2.908 4.394 4.548 2.816 4.394 4.548 92 0 0 2.921 3.023 3.133 4.00 4.483 4.643 4.727 4.814 Max Units V V V V V V mV mV mV V V V V V V V V V V V V V V V V V V Vdd Value for PPOR Trip (positive ramp) VPPOR0R PORLEV[1:0] = 00b VPPOR1R PORLEV[1:0] = 01b VPPOR2R PORLEV[1:0] = 10b VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b - - - - - - - 2.863 2.963 3.070 3.920 4.393 4.550 4.632 4.718 - - - 2.979a 3.083 3.196 4.080 4.573 4.736b 4.822 4.910 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 2.963 3.033 3.185 4.110 4.550 4.632 4.719 4.900 3.023 3.095 3.250 4.194 4.643 4.727 4.815 5.000 3.083 3.157 3.315 4.278 4.736 4.822 4.911 5.100 a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 38-12011 Rev. *G Page 25 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 24. DC Programming Specifications Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total)a Flash Data Retention Min - - 2.2 - - - Vdd - 1.0 50,000 1,800,000 10 Typ 5 - - - - - - - - - Max 25 0.8 - 0.2 1.5 Vss + 0.75 Vdd - - - Units mA V V mA mA V V - Erase/write cycles per block. - Erase/write cycles. Years Driving internal pull down resistor. Driving internal pull down resistor. Notes a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 38-12011 Rev. *G Page 26 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 25. AC Chip-Level Specifications Symbol FIMO FCPU1 FCPU2 F48M F24M F32K1 F32K2 Description Internal Main Oscillator Frequency CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator Min 23.4 0.93 0.93 0 0 15 - Typ 24 24 12 48 Max 24.6a 24.6a,b 12.3b,c 49.2a,b,d Units MHz MHz MHz MHz MHz kHz kHz Notes Trimmed. Using factory trim values. Refer to the AC Digital Block Specifications. 24 24.6b,e,d 32 64 32.768 - FPLL Jitter24M2 TPLLSLEW TPLLSLEWSLOW TOS TOSACC Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP PLL Frequency 24 MHz Period Jitter (PLL) PLL Lock Time PLL Lock Time for Low Gain Setting External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Maximum frequency of signal on row input or row output. Supply Ramp Time - - 0.5 0.5 - - - 10 40 - 46.8 - - 0 23.986 - - - 1700 2800 100 - 50 50 48.0 600 - - - 600 10 50 2620 3800f - 60 - 49.2a,c MHz ps ms ms ms ms ns s % kHz MHz ps MHz s Accuracy is capacitor and crystal dependent. 50% duty cycle. Is a multiple (x732) of crystal frequency. Trimmed. Using factory trim values. 12.3 - a. 4.75V < Vdd < 5.25V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. d. See the individual user module data sheets for information on maximum frequencies for user modules. e. 3.0V < 5.25V. f. The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V Vdd 5.5V, -40 oC TA 85 oC. Document Number: 38-12011 Rev. *G Page 27 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Figure 12. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 13. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 14. External Crystal Oscillator Startup Timing Diagram 32K Select TOS 32 kHz F32K2 Figure 15. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F24M Figure 16. 32 kHz Period Jitter (ECO) Timing Diagram Jitter32k F32K2 Document Number: 38-12011 Rev. *G Page 28 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 26. AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 10 10 Typ - - - 27 22 Max 12 18 18 - - Units MHz ns ns ns ns Notes Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Figure 17. GPIO Timing Diagram 90% GPIO Pin 10% TRiseF TRiseS TFallF TFallS Document Number: 38-12011 Rev. *G Page 29 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 27. 5V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High Falling Slew Rate(20% to 80%) (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High Gain Bandwidth Product Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min Typ Max Units s s s s s s s s s s s s - - - - - - - - - 3.9 0.72 0.62 Notes Specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. Specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. TSOA - - - - - - 0.15 1.7 6.5 0.01 0.5 4.0 0.75 3.1 5.4 - - - - - - - - - - - - - 200 5.9 0.92 0.72 SRROA V/s V/s V/s V/s V/s V/s V/s V/s V/s V/s V/s V/s MHz MHz MHz MHz MHz MHz nV/rt-Hz SRFOA BWOA ENOA - Document Number: 38-12011 Rev. *G Page 30 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Table 28. 3.3V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High (3.3 Volt High Bias Operation not supported) Power = High, Opamp Bias = High (3.3 Volt High Power, High Opamp Bias not supported) Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High (3.3 Volt High Bias Operation not supported) Power = High, Opamp Bias = High (3.3 Volt High Power, High Opamp Bias not supported) Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High (3.3 Volt High Bias Operation not supported) Power = High, Opamp Bias = High (3.3 Volt High Power, High Opamp Bias not supported) Falling Slew Rate(20% to 80%) (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High (3.3 Volt High Bias Operation not supported) Power = High, Opamp Bias = High (3.3 Volt High Power, High Opamp Bias not supported) Gain Bandwidth Product Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High (3.3 Volt High Bias Operation not supported) Power = High, Opamp Bias = High (3.3 Volt High Power, High Opamp Bias not supported) Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min Typ Max Units s s s s s s - - - - - - - - - - 3.92 0.72 - - Notes Specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. TSOA - - - - - - - - - - 5.41 0.72 - - s s s s s s Specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. SRROA 0.31 2.7 - - - - - - - - V/s V/s V/s V/s V/s V/s Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. SRFOA 0.24 1.8 - - - - - - - - V/s V/s V/s V/s V/s V/s Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. BWOA 0.67 2.8 - - - - - - - 200 - - - MHz MHz MHz MHz MHz MHz nV/rt-Hz Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. ENOA Document Number: 38-12011 Rev. *G Page 31 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 29. AC Digital Block Specifications Function Timer Description Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Maximum Input Clock Frequency Maximum Input Clock Frequency 20 50a 50a - - - - - 50a - - - - - - - - - - - - 16 - - - 49.2 49.2 24.6 8.2 4.1 - 16.4 49.2 ns ns ns MHz MHz MHz MHz ns ns MHz MHz 4.75V < Vdd < 5.25V 4.75V < Vdd < 5.25V 4.75V < Vdd < 5.25V Min 50 - - 50a - - a Typ - - - - - - Max - 49.2 24.6 - 49.2 24.6 Units ns MHz MHz ns MHz MHz Notes 4.75V < Vdd < 5.25V 4.75V < Vdd < 5.25V a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 38-12011 Rev. *G Page 32 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 30. 5V AC Analog Output Buffer Specifications Symbol TROB Description Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min - - - - 0.65 0.65 0.65 0.65 0.8 0.8 300 300 Typ - - - - - - - - - - - - Max 2.5 2.5 2.2 2.2 - - - - - - - - Units s s s s TSOB SRROB V/s V/s V/s V/s MHz MHz kHz kHz SRFOB BWOB BWOB Table 31. 3.3V AC Analog Output Buffer Specifications Symbol TROB Description Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min - - - - 0.5 0.5 0.5 0.5 0.7 0.7 200 200 Typ - - - - - - - - - - - - Max 3.8 3.8 2.6 2.6 - - - - - - - - Units s s s s TSOB SRROB V/s V/s V/s V/s MHz MHz kHz kHz SRFOB BWOB BWOB Document Number: 38-12011 Rev. *G Page 33 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 32. 5V AC External Clock Specifications Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description Min 0 20.6 20.6 150 Typ - - - - Max 24.24 - - - Units MHz ns ns s Table 33. 3.3V AC External Clock Specifications Symbol FOSCEXT FOSCEXT - - - Description Frequency with CPU Clock divide by 1a Frequency with CPU Clock divide by 2 or greaterb High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch Min 0 0 41.7 41.7 150 Typ - - - - - Max 12.12 24.24 - - - Units MHz MHz ns ns s a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 34. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Min 1 1 40 40 0 - - - Typ - - - - - 15 30 - Max 20 20 - - 8 - - 45 Units ns ns ns ns MHz ms ms ns Document Number: 38-12011 Rev. *G Page 34 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 35. AC Characteristics of the I2C SDA and SCL Pins Symbol Description Standard Mode Min Max 0 100 4.0 - 4.7 4.0 4.7 0 250 4.0 4.7 - - - - - - - - - Fast Mode Min Max 0 400 0.6 - 1.3 0.6 0.6 0 100a 0.6 1.3 0 - - - - - - - 50 Units kHz s s s s s ns s s ns FSCLI2C SCL Clock Frequency THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. TLOWI2C LOW Period of the SCL Clock THIGHI2C HIGH Period of the SCL Clock TSUSTAI2C Setup Time for a Repeated START Condition THDDATI2C Data Hold Time TSUDATI2C Data Setup Time TSUSTOI2C Setup Time for STOP Condition TBUFI2C Bus Free Time Between a STOP and START Condition TSPI2C Pulse Width of spikes are suppressed by the input filter. a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Figure 18. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C Sr P S Document Number: 38-12011 Rev. *G Page 35 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Packaging Information This section presents the packaging specifications for the CY8C24x23 PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Figure 19. 8-Pin (300-Mil) PDIP 51-85075 *A Document Number: 38-12011 Rev. *G Page 36 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Figure 20. 8-Pin (150-Mil) SOIC 51-85066 *B 51-85066 *C Figure 21. 20-Pin (300-Mil) Molded DIP ( ) 51-85011-A 51-85011 *A Document Number: 38-12011 Rev. *G Page 37 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Figure 22. 20-Pin (210-Mil) SSOP 51-85077 *C Figure 23. 20-Pin (300-Mil) Molded SOIC 51-85024 *C Document Number: 38-12011 Rev. *G Page 38 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Figure 24. 28-Pin (300-Mil) Molded DIP 51-85014 *D Document Number: 38-12011 Rev. *G Page 39 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Figure 25. 28-Pin (210-Mil) SSOP 51-85079 *C Figure 26. 28-Pin (300-Mil) Molded SOIC 51-85026 *D Document Number: 38-12011 Rev. *G Page 40 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Figure 27. 32-Pin (5x5 mm) MLF 51-85188 *B Thermal Impedances Table 36. Thermal Impedances per Package Package 8 PDIP 8 SOIC 20 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 32 MLF * TJ = TA + POWER x JA Capacitance on Crystal Pins Table 37. Typical Package Capacitance on Crystal Pins Package 8 PDIP 8 SOIC 20 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 32 MLF Package Capacitance 2.8 pF 2.0 pF 3.0 pF 2.6 pF 2.5 pF 3.5 pF 2.8 pF 2.7 pF 2.0 pF Typical JA * 123 oC/W 185 oC/W o 109 oC/W 117 C/W 81 oC/W 69 74 oC/W oC/W 101 oC/W 22 oC/W Document Number: 38-12011 Rev. *G Page 41 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Ordering Information The following table lists the CY8C24x23 PSoC Device family's key package features and ordering codes. Table 38. CY8C24x23 PSoC Device Family Key Features and Ordering Information Analog Outputs 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Analog Blocks (Columns of 3) Digital IO Pins Analog Inputs Digital Blocks (Rows of 4) Switch Mode Pump Temperature Range 8 Pin (300 Mil) DIP 8 Pin (150 Mil) SOIC 8 Pin (150 Mil) SOIC (Tape and Reel) 20 Pin (300 Mil) DIP 20 Pin (210 Mil) SSOP 20 Pin (210 Mil) SSOP (Tape and Reel) 20 Pin (300 Mil) SOIC 20 Pin (300 Mil) SOIC (Tape and Reel) 28 Pin (300 Mil) DIP 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) 28 Pin (300 Mil) SOIC 28 Pin (300 Mil) SOIC (Tape and Reel) 32 Pin (5x5 mm) MLF CY8C24123-24PI CY8C24123-24SI CY8C24123-24SIT CY8C24223-24PI CY8C24223-24PVI CY8C24223-24PVIT CY8C24223-24SI CY8C24223-24SIT CY8C24423-24PI CY8C24423-24PVI CY8C24423-24PVIT CY8C24423-24SI CY8C24423-24SIT CY8C24423-24LFI 4 4 4 4 4 4 4 4 4 4 4 4 4 4 256 256 256 256 256 256 256 256 256 256 256 256 256 256 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 16 16 16 16 16 24 24 24 24 24 24 4 4 4 8 8 8 8 8 10 10 10 10 10 10 No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). Ordering Code Definitions CY 8 C 24 xxx-SPxx Package Type: P = PDIP S = SOIC PV = SSOP LF = MLF A = TQFP Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress MicroSystems Company ID: CY = Cypress Thermal Rating: C = Commercial I = Industrial E = Extended Document Number: 38-12011 Rev. *G Page 42 of 43 XRES Pin Ordering Code Package Flash (Kbytes) RAM (Bytes) [+] Feedback CY8C24123 CY8C24223, CY8C24423 Document History Page Document Title: CY8C24123, CY8C24223, CY8C24423 PSoC(R) Programmable System-on-ChipTM Document Number: 38-12011 Revision ** *A *B *C *D *E *F ECN 127043 128779 129775 130128 131678 131802 229418 Orig. of Change New Silicon and NWJ NWJ MWR/NWJ NWJ NWJ NWJ SFV Submission Date 05/15/2003 08/13/2003 09/26/2003 10/14/2003 12/04/2003 12/22/2003 06/04/2004 Description of Change New document - Advanced Data Sheet (two page product brief). New document - Preliminary Data Sheet (300 page product detail). Changes to Electrical Specifications section, Register Details chapter, and chapter changes in the Analog System section. Revised document for Silicon Revision A. Changes to Electrical Specifications section, Miscellaneous changes to I2C, GDI, RDI, Registers, and Digital Block chapters. Changes to Electrical Specifications and miscellaneous small changes throughout the data sheet. New data sheet format and organization. Reference the PSoC Programmable System-on-Chip Technical Reference Manual for additional information. Title change. Changed title to "CY8C24123, CY8C24223, CY8C24423 PSoC(R) Programmable System-on-ChipTM" Updated package diagrams 51-85188, 51-85024, 51-85014, and 51-85026. Added note on digital signaling in Table on page 23. Added Die Sales information note to Ordering Information on page 42. Updated data sheet template. *G 2619935 ONGE/AESA 12/11/2008 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-12011 Rev. *G Revised December 11, 2008 Page 43 of 43 PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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